PCS/FEC#
PCS (Physical Coding Sublayer) and FEC (Forward Error Correction) are two essential components of the Ethernet standard that work together to ensure reliable and error-free data transmission over Ethernet networks. These components are primarily associated with the Ethernet physical layer, which is Layer 1 of the OSI model.
Fig. 79 Port Properties - PCS/FEC#
At the top of the page you can Enable Forward Error Correction (FEC) if that is supported by the port.
Important
For PAM4 ports, FEC is mandatory.
Clear Counters will clear the counters on the page and by checking Allow clearing counters from Global view you can use the clear counters facilities in the Global Statistics pages to clear the counters in this page.
What is shown on the rest of this page depends on the configuration of the selected port.
PCS Variant#
Note
Only available on Freya module.
Both IEEE and ETC (Ethernet Technology Consortium) have specifications for 100 Gb/s lane rate based 800GbE:
IEEE: 800GBASE-CR8/KR8
ETC: 800G-ETC-CR8/KR8
When testing with 800G on Freya using ValkyrieManager, you can either manually configure the 800G variant by selecting IEEE or ETC in as shown below, or let auto-negotiation decide.
Fig. 80 Port Properties - PCS/FEC - PCS Variant#
PAM4 (56G and 112G Serdes Lane) Ports#
The image below shows what you can see on a PAM4 port, in this case a 200GE 56G serdes port on Freya module:
Fig. 81 Port Properties - PCS/FEC (200GE 56G serdes port on Freya module)#
In the Transmit Configuration section you can for each physical Lane on the port see the SerDes, and Lane. You can change the Virtual Lane used for the physical lane and set Skew Bits for each lane.
In the Receive Status section you can for each physical Lane see if it is in Align Lock (Alignment lock), the Virtual Lane used for the physical lane and set Skew Bits for each lane. In addition, you for each lane can see number of Corrected Bit Errors and the estimated Pre-FEC BER.
The lower part of the page contains FEC statistics for the port:
Total corrected FEC Symbols
Total uncorrected FEC blocks
Estimated Pre-FEC BER
Estimated Post-FEC BER
You will also find the Pre-FEC Error Distribution graph. Here you can see number of received FEC blocks with 0, 1, 2.. up to 15 symbol errors. This is what the RS-FEC used for PAM4 signals will correct. You can also see number of received FEC blocks with more than 15 symbol errors. This is more than the RS-FEC used for PAM4 signals can correct so this will cause uncorrected FEC blocks to be counted and most likely also cause errors at higher layers in the received signal.
Note
Freya module supports RS-FEC Int, which is specified in IEEE 802.3ck CL 161. When Freya port is configured to 100GBASE (with 112 serdes speed), the option of RS-FEC Int will be enabled for selection in
Note
Error injection is currently not implemented.
NRZ Ports (25G Serdes Lane) With FEC#
The image below shows what you can see on a NRZ port with FEC, in this case a 100G port.
Fig. 82 Port Properties - PCS/FEC (NRZ Ports w/ FEC)#
Most is similar to what you can control and see for PAM4 ports. Please also observe that the RS-FEC used for NRZ signals will correct up to 7 symbol errors. The Pre-FEC Error Distribution graph is adjusted accordingly.
Some ports also support Firecode FEC when running at 10G and 25G NRZ.
Note
Port speeds of 10G/25G on Loki and Thor support Firecode FEC.
NRZ Ports (25G Serdes Lane) No FEC#
The image below shows what you can see on a NRZ port without FEC, in this case a 100G port.
Fig. 83 Port Properties - PCS/FEC (NRZ Ports w/o FEC)#
Most is similar to what you can control and see for PAM4 ports in the Transmit Configuration and Receive Status tables. Please observe however that in the Receive Status table you can see additional counters for Header Errors, Alignment Errors. The Corrected Bit Errors and the Pre-FEC BER counters are not updated for ports without RS-FEC.
Note
Port speeds of 10G/25G on Loki and Thor support Firecode FEC.