PL1_PHYTXEQ

code: 442

Attention

The following modules are supported:

  • Xena Freya

  • Xena Edun

# set
<module-index>/<port-index> PL1_PHYTXEQ [<serdes_index>] <eq_values>

# get
<module-index>/<port-index> PL1_PHYTXEQ [<serdes_index>] ?

Description

Control the host-side equalizer settings per SerDes.

Note

PL1_PHYTXEQ, PL1_PHYTXEQ_LEVEL, and PL1_PHYTXEQ_COEFF facilitate the configuration and retrieval of Tx tap values, each offering a unique perspective. Modifications made with any of these parameters will result in updates to the read results across all of them.

Actions

set, get

Parameters

  1. eq_values: list of integers, the list of equalizer values in the order of preN, …, pre2, pre1, main, post1, post2, …, postM. The number of pre taps, N = P_CAPABILITIES.num_txeq_pre. The number of post taps, M = P_CAPABILITIES.num_txeq - P_CAPABILITIES.num_txeq_pre - 1.

Rules for Z800 Freya Modules

PAM4, 5-tap mode

  • Default value of pre and post equalizers is 0.

  • Absolute sum limit is 87.

Rules for Z1608 Edun Modules

PAM4, 6-tap mode

  • main TAP is expected to be positive and pre1 and post1 TAPs are expected to be negative.

  • main TAP is expected to be greater than all other TAPs.

  • pre3 TAP is expected to be within [-12,0].

  • Absolute sum limit is 168.

Rules for Z1604 Edun Modules

PAM4, 7-tap mode

  • Range for all TAPs is -168..168

  • Absolute sum limit is 168.

Example

FREYA-800G-4S-1P

# set
input:  0/1 PL1_PHYTXEQ [0] 1 4 5 80 3
output: <OK>

# get
input:  0/1 PL1_PHYTXEQ [0] ?
output: 0/1 PL1_PHYTXEQ [0] 1 4 5 80 3

EDUN-800G-3S-1P-SMPX

# set
input:  0/1 PL1_PHYTXEQ [0] 0 0 160 0 0 0 0
output: <OK>

# get
input:  0/1 PL1_PHYTXEQ [0] ?
output: 0/1 PL1_PHYTXEQ [0] 0 0 160 0 0 0 0